This invention relates to methods and systems used for generating behavioral models used in integrated circuit design. More particularly, the present invention provides for a new behavioral model that provides timing, noise and integrity grid analysis.
When simulating I/O electrical performance during timing characterization, signal integrity analysis, and power grid integrity analysis, various I/O modeling techniques have been used. At one end of the modeling spectrum are the full netlist models that contain detailed architectural and parasitic information of the I/O. These models provide the highest level of accuracy and can be used for a variety of analysis. A major disadvantage of full netlist models are excessive simulation times that prohibit them from being used at the chip level and non-convergence under certain conditions. At the other end of the spectrum are empirical models for driver delay and IBIS models for signal integrity analysis.
Empirical models use simple equations or lookup tables for predicting driver delay and output slew rate. The advantage of empirical models is fast simulation time. The disadvantages are poor accuracy under certain conditions, and they are typically limited to timing analysis. For signal integrity analysis IBIS models can be used. The advantage of these models are accurate driver output waveforms across a wide range of loading conditions. The disadvantages are they cannot be used for timing analysis and the models do not predict driver sensitivity to variations in supply voltage, temperature, and input slew rate.
I/O behavioral modeling in the form of IBIS models has gained wide acceptance in signal integrity analysis. While the IBIS model accurately represents the characteristics of the output pin at three fixed process corners, it does not model driver delay or account for variations in temperature, supply voltages, and input transition rate. The IBIS models used today by various board level simulation tools for signal integrity analysis are behavioral in nature and offer the user and developer of the models several advantages over full-netlist models. First, because IBIS models are behavioral, they contain no proprietary information. This makes it easy to exchange information about I/O characteristics without disclosing intellectual property. Second, behavioral simulation is faster than full-netlist simulation (e.g., Spice) because it uses higher-level abstraction models. What would be prohibitive in terms of simulation time when using full-netlist models can be accomplished in reasonable time with behavioral models.
The IBIS specification (ANSI/EIA-656-A, “I/O Buffer Information Specification (IBIS) Version 3.2”, September 1999), presents several techniques for improving model accuracy across a wide range of I/O family types for signal integrity analysis. I/O behavior modeling (e.g. IBIS I/O Buffer Information Specification) have been used by industry in PCB level signal integrity tools such as SpectraQuest from Cadence and XTK from Viewlogic for several years.